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LTC4252-1/LTC4252-2 Negative Voltage Hot Swap Controllers
FEATURES
s s
DESCRIPTIO
s
s s s
s s s
Allows Safe Board Insertion and Removal from a Live - 48V Backplane Floating Topology Permits Very High Voltage Operation Programmable Analog Current Limit With Circuit Breaker Timer Fast Response Time Limits Peak Fault Current Programmable Soft-Start Current Limit Programmable Timer with Drain Voltage Accelerated Response Programmable Undervoltage/Overvoltage Protection LTC4252-1: Latch Off After Fault LTC4252-2: Automatic Retry After Fault
The LTC(R)4252 negative voltage Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. Programmable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The LTC4252's supply input is shunt regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial startup and controls the circuit breaker's response time. The circuit breaker's response time is accelerated by sensing excessive MOSFET drain voltage, keeping the MOSFET within its safe operating area (SOA). A programmable soft-start circuit controls MOSFET inrush current at startup. A power good status output can enable a power module at start-up or disable it if the circuit breaker trips. The LTC4252-1 latches off after a circuit breaker fault times out. The LTC4252-2 provides automatic retry after a fault. The LTC4252 is available in either an 8-pin or 10-pin MSOP.
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
APPLICATIO S
s s s s s s s s
Hot Board Insertion Electronic Circuit Breaker - 48V Distributed Power Systems Negative Power Supply Control Central Office Switching Programmable Current Limiting Circuit High Availability Servers Disk Arrays
TYPICAL APPLICATIO
GND
- 48V/2.5A Hot Swap Controller
RIN 3x 1.8k IN SERIES 1/4W EACH CIN 1F
+
CL 100F LOAD EN
GATE 5V/DIV
GND (SHORT PIN)
1 R1 402k 1% VIN LTC4252-1 8 9 R2 32.4k 1% C1 10nF 10 OV UV PWRGD DRAIN GATE VEE 5 SENSE 2 7 6 4
R3 5.1k * RD 1M VOUT
SENSE 2.5A/DIV
TIMER 3 CT SS 0.33F CSS 68nF
Q1 IRF530S RC 10 CC 18nF RS 0.02
VOUT 20V/DIV
-48V * M0C207
4252-1/2 TA01
PWRGD 10V/DIV 1ms/DIV
4252-1/2 TA01a
U
Start-Up Behavior
425212f
U
U
1
LTC4252-1/LTC4252-2
ABSOLUTE
AXI U RATI GS
Current into VIN (100s Pulse) ........................... 100mA VIN, DRAIN Pin Minimum Voltage ....................... - 0.3V Input/Output Pins (Except SENSE and DRAIN) Voltage ..........- 0.3V to 16V SENSE Pin Voltage ................................... - 0.6V to 16V Current Out of SENSE Pin (20s Pulse) ........... - 200mA Current into DRAIN Pin (100s Pulse) ................. 20mA
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW VIN SS SENSE VEE 1 2 3 4 8 7 6 5 TIMER UV/OV DRAIN GATE
LTC4252-1CMS8 LTC4252-2CMS8 LTC4252-1IMS8 LTC4252-2IMS8 MS8 PART MARKING LTWM LTWP LTRQ LTRR
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 160C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
SYMBOL VZ rZ IIN VLKO VLKH VCB VACL VFCL VSS RSS ISS VOS PARAMETER VIN - VEE Zener Voltage VIN - VEE Zener Dynamic Impedance VIN Supply Current VIN Undervoltage Lockout VIN Undervoltage Lockout Hysteresis Circuit Breaker Current Limit Voltage Analog Current Limit Voltage Fast Current Limit Voltage SS Voltage SS Output Impedance SS Pin Current Analog Current Limit Offset Voltage UV = OV = 4V, VSENSE = VEE, VSS = 0V (Sourcing) UV = OV = 0V, VSENSE = VEE, VSS = 2V (Sinking) VCB = (VSENSE - VEE) VACL = (VSENSE - VEE), SS = Open or 2.2V VFCL = (VSENSE - VEE) After End of SS Timing Cycle
q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS IIN = 2mA IIN = 2mA to 30mA UV = OV = 4V, VIN = (VZ - 0.3V) Coming Out of UVLO (Rising VIN)
q q q
VACL+VOS Ratio (VACL + VOS) to SS Voltage VSS
2
U
U
W
WW
U
W
All Voltages Referred to VEE (Note 1)
Maximum Junction Temperature .......................... 125C Operating Temperature Range LTC4252-1C/LTC4252-2C ....................... 0C to 70C LTC4252-1I/LTC4252-2I ................... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER
TOP VIEW VIN PWRGD SS SENSE VEE 1 2 3 4 5 10 9 8 7 6 TIMER UV OV DRAIN GATE
LTC4252-1CMS LTC4252-2CMS LTC4252-1IMS LTC4252-2IMS MS PART MARKING LTWN LTWQ LTRS LTRT
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 160C/W
MIN 12
TYP 13 5 0.8 9.2 1
MAX 14.5 2 12 60 120 300
UNITS V mA V V mV mV mV V k A mA mV V/V
425212f
40 80 150
50 100 200 2.2 100 22 28 10 0.05
LTC4252-1/LTC4252-2
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
SYMBOL IGATE PARAMETER GATE Pin Output Current CONDITIONS UV = OV = 4V, VSENSE = VEE, VGATE = 0V (Sourcing) UV = OV = 4V, VSENSE - VEE = 0.15V, VGATE = 3V (Sinking) UV = OV = 4V, VSENSE - VEE = 0.3V, VGATE = 1V (Sinking) VGATE VGATEH VGATEL VUVHI VUVLO VUVHST VOVHI VOVLO VOVHST ISENSE IINP VTMRH VTMRL ITMR External MOSFET Gate Drive Gate High Threshold Gate Low Threshold UV Pin Threshold HIGH UV Pin Threshold LOW UV Pin Hysteresis OV Pin Threshold HIGH OV Pin Threshold LOW OV Pin Hysteresis SENSE Pin Input Current UV, OV Pin Input Current TIMER Pin Voltage High Threshold TIMER Pin Voltage Low Threshold TIMER Pin Current Timer On (Initial Cycle/Latchoff/ Shutdown Cooling, Sourcing), VTMR = 2V Timer Off (Initial Cycle, Sinking), VTMR = 2V Timer On (Circuit Breaker, Sourcing, IDRN = 0A), VTMR = 2V Timer On (Circuit Breaker, Sourcing, IDRN = 50A), VTMR = 2V Timer Off (Circuit Breaker/ Shutdown Cooling, Sinking), VTMR = 2V ITMRACC [(ITMR at IDRN = 50A) - (ITMR at IDRN = 0A)] IDRN 50A VDRNL IDRNL VDRNCL VPGL IPGH tSS tPLLUG tPHLOG DRAIN Pin Voltage Low Threshold DRAIN Leakage Current DRAIN Pin Clamp Voltage PWRGD Output Low Voltage PWRGD Pull-Up Current SS Default Ramp Period UV Low to Gate Low OV High to Gate Low Timer On (Circuit Breaker with IDRN = 50A) For PWRGD Status (MS Only) VDRAIN = 5V IDRN = 50A IPG = 1.6mA (MS Only) IPG = 5mA (MS Only) VPWRGD = 0V (Sourcing) (MS Only) SS pin floating, VSS ramps from 0.2V to 2V
q q q q q q
ELECTRICAL CHARACTERISTICS
MIN 40
TYP 58 17 190
MAX 80
UNITS A mA mA
VGATE - VEE, IIN = 2mA VGATEH = VIN - VGATE, IIN = 2mA, for PWRGD Status (MS Only) (Before Gate Ramp-Up)
q
10
12 2.8 0.5
VZ
V V V
q q
3.075 2.775 5.85 5.25 -30
3.225 2.925 0.3 6.15 5.55 0.6 -15 0.1 4 1 5.8 28 230 630 5.8 8 2.385 0.1 7 0.2
3.375 3.075 6.45 5.85
V V V V V V A
UV = OV = 4V, VSENSE = 50mV UV = OV = 4V
q q
10
A V V A mA A A A A/A V
1 0.4 1.1 80
A V V V A s s s
40
58 180 0.4 0.4
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VEE unless otherwise specified.
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3
LTC4252-1/LTC4252-2 TYPICAL PERFOR A CE CHARACTERISTICS
VZ vs Temperature
14.5 IIN = 2mA
14.0
6 5 4
IIN (A)
13.5
VZ (V)
rZ ()
13.0
12.5
12.0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G04
IIN vs VIN
1000
TA = -40C 100 TA = 25C
VLKO (V)
10
TA = 85C TA = 125C
10.0 9.5
VLKH (V)
IIN (mA)
1
0.1
0
2
4
6
8 10 12 14 16 18 20 22 VIN (V)
4252-1/2 G02
Circuit Breaker Current Limit Voltage VCB vs Temperature
60 58 56 54
VACL (mV)
50 48 46 44 42 40 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G07
100 95 90 85 80 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G08
VFCL (mV)
VCB (mV)
52
4
UW
rZ vs Temperature
10 9 8 7 IIN = 2mA
2000 1800 1600 1400 1200 1000 800 600 400 200
IIN vs Temperature
VIN = (VZ - 0.3V)
3 2 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G03
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G01
Undervoltage Lockout VLKO vs Temperature
12.0 11.5 11.0 10.5
Undervoltage Lockout Hysteresis VLKH vs Temperature
1.5
1.3
1.1
0.9
9.0
0.7
8.5 8.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G05
0.5 -55 -35 -15
5 25 45 65 95 105 125 TEMPERATURE (C)
4252-1/2 G06
Analog Current Limit Voltage VACL vs Temperature
120 115 110 105 250 225 200 175 300 275
Fast Current Limit Voltage VFCL vs Temperature
150 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G09
425212f
LTC4252-1/LTC4252-2 TYPICAL PERFOR A CE CHARACTERISTICS
VSS vs Temperature
2.40 2.35 2.30 RSS (k) 2.25
VSS (V)
ISS (mA)
2.20 2.15 2.10 2.05 2.00 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G26
VOS vs Temperature
11.0 10.8 10.6 10.4 VOS (mV) 10.2 10.0 9.8 9.6 9.4 9.2 9.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G29
(VACL + VOS) / VSS (V/V)
0.052 0.050 0.048 0.046 0.044 0.042 0.040 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G30
IGATE (A)
IGATE (ACL, Sinking) vs Temperature
30 25 20
IGATE (mA) IGATE (mA)
UV/0V = 4V TIMER = 0V VSENSE - VEE = 0.15V VGATE = 3V
VGATE (V)
15 10 5 0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G11
UW
RSS vs Temperature
110 108 106 104 102 100 98 96 94 92 90 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G28
ISS (Sinking) vs Temperature
45 40 35 30 25 20 15 10 5 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G39
UV = OV = VSENSE = VEE IIN = 2mA VSS = 2V
(VACL + VOS)/VSS vs Temperature
0.060 0.058 0.056 0.054
70
IGATE (Sourcing) vs Temperature
UV/0V = 4V TIMER = 0V 65 VSENSE = VEE VGATE = 0V 60 55 50 45 40 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G10
IGATE (FCL, Sinking) vs Temperature
400 350 300 250 200 150 100 50 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G12
VGATE vs Temperature
14.5 UV/0V = 4V 14.0 TIMER = 0V VSENSE = VEE 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G13
UV/0V = 4V TIMER = 0V VSENSE - VEE = 0.3V VGATE = 1V
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5
LTC4252-1/LTC4252-2 TYPICAL PERFOR A CE CHARACTERISTICS
VGATEH vs Temperature
3.6 3.4 3.2 VGATEH (V) VGATEL (V) 3.0 2.8 2.6 2.4 2.2 2.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G31
VGATEH = VIN - VGATE, IIN = 2mA (MS ONLY)
UV THRESHOLD (V)
OV Threshold vs Temperature
6.45 6.25 OV THRESHOLD (V) 6.05
ISENSE (A)
VOVH
-18 -20 -22 -24 -26 -28 UV/0V = 4V TIMER = 0V GATE = HIGH VSENSE - VEE = 50mV 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G17
-ISENSE (mA)
5.85 5.65 5.45 5.25 -55 -35 -15
VOVL
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G16
TIMER Threshold vs Temperature
5.0 4.5 4.0
TIMER THRESHOLD (V)
VTMRH
3.5
ITMR (mA)
ITMR (A)
3.0 2.5 2.0 1.5 1.0 0.5 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G19
VTMRL
6
UW
VGATEL vs Temperature
0.8 UV/0V = 4V 0.7 TIMER = 0V GATE THRESHOLD 0.6 BEFORE RAMP-UP 0.5 0.4 0.3 0.2 0.1 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G14
UV Threshold vs Temperature
3.375 3.275 3.175 3.075 2.975 2.875 2.775 -55 -35 -15
VUVH
VUVL
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G15
ISENSE vs Temperature
-10 -12 -14 -16 1.0 0.1 0.01
ISENSE vs (VSENSE - VEE)
10 UV/0V = 4V TIMER = 0V GATE = HIGH TA = 25C 1.5 2.0
100
-30 -55 -35 -15
1000 -1.5 -1.0 -0.5 0 0.5 1.0 (VSENSE - VEE) (V)
4252-1/2 G18
ITMR (Initial Cycle, Sourcing) vs Temperature
10 9 8 7 6 5 4 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G20
ITMR (Initial Cycle, Sinking) vs Temperature
50 TIMER = 2V 45 40 35 30 25 20 15 10 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G21
TIMER = 2V
425212f
LTC4252-1/LTC4252-2 TYPICAL PERFOR A CE CHARACTERISTICS
ITMR (Circuit Breaker, Sourcing) vs Temperature
280 690 TIMER = 2V IDRN = 0A 670 650
ITMR (A)
260
ITMR (A)
630 610 590
ITMR (A)
240
220
200 570 180 -55 -35 -15 550 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G22
ITMR vs IDRN
10 9.0 8.8 ITMRACC/IDRN (A/A) 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 0.1 0.001 0.01 0.1 IDRN (mA) 1 10
4252-1/2 G33
ITMR (mA)
IDRN (mA)
1
VDRNL vs Temperature
2.60 FOR PWRGD STATUS (MS ONLY) 2.55 2.50 VDRNCL (V) VDRNL (V) 2.45 2.40 2.35 2.30 2.25 2.20 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G35
7.0 6.8 6.6 6.4 6.2 6.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G36
VPGL (V)
UW
ITMR (Circuit Breaker, IDRN = 50A, Sourcing) vs Temperature
TIMER = 2V IDRN = 50A
10 9 8 7 6 5 4 3 2 1
ITMR (Cooling Cycle, Sinking) vs Temperature
TIMER = 2V
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G32
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G23
ITMRACC/IDRN vs Temperature
100
TIMER ON (CIRCUIT BREAKING, IDRN = 50A)
IDRN vs VDRAIN
IIN = 2mA
10 1 0.1 0.01 TA = 125C TA = 85C 0.001 0.0001 0.00001 TA = 25C 0 2 4 6
TA = -40C 8 10 VDRAIN (V) 12 14 16
7.0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G34
4252-1/2 G25
VDRNCL vs Temperature
8.0 7.8 7.6 7.4 7.2 2.5 2.0 1.5 1.0 0.5 IDRN = 50A 3.0
VPGL vs Temperature
(MS ONLY)
IPG = 10mA
IPG = 5mA
IPG = 1.6mA 5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G37
0 -55 -35 -15
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7
LTC4252-1/LTC4252-2 TYPICAL PERFOR A CE CHARACTERISTICS
IPGH vs Temperature
62 61 60 VPWRGD = 0V (MS ONLY)
tSS (s)
59 58 57 56 55 -55 -35 -15
190 180 170 160 150 -55 -35 -15
DELAY (s)
IPGH (A)
5 25 45 65 85 105 125 TEMPERATURE (C) 4252-1/2 G38
PI FU CTIO S
(MS/MS8)
VIN (Pin 1/Pin 1): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator clamps VIN at 13V. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (9.2V), overriding UV and OV. If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating a GATE ramp-up. If VIN drops below approximately 8.2V, GATE pulls low immediately. PWRGD (Pin 2/Not Available): Power Good Status Output (MS only). At start-up, PWRGD latches low if DRAIN is below 2.385V and GATE is within 2.8V of VIN. PWRGD status is reset by UV, VIN (UVLO) or a circuit breaker fault timeout. This pin is internally pulled high by a 58A current source. SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/dt. A 20x attenuated version of the SS pin voltage is presented to the current limit amplifier. This attenuated voltage limits the MOSFET's drain current through the sense resistor during the soft-start current limiting. At the beginning of a start-up cycle, the SS capacitor (CSS) is ramped by a 22A current source. The GATE pin is held
8
UW
tSS vs Temperature
220 210 200 SS PIN FLOATING, VSS RAMPS FROM 0.2V TO 2V
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
tPLLUG and tPHLOG vs Temperature
tPLLUG tPHLOG
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G27
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4252-1/2 G24
U
U
U
low until SS exceeds 20 * VOS = 0.2V. SS is internally shunted by a 100k resistor (RSS) which limits the SS pin voltage to 2.2V. This corresponds to an analog current limit SENSE voltage of 100mV. If the SS capacitor is omitted, the SS pin ramps from 0V to 2.2V in about 220s. The SS pin is pulled low under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (230A+8*IDRN) TIMER pull-up current. If SENSE exceeds VACL (100mV), the analog current limit amplifier pulls GATE down to regulate the MOSFET current at VACL/RS. In the event of a catastrophic short-circuit, SENSE may overshoot 100mV. If SENSE reaches VFCL (200mV), the fast current limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE.
425212f
LTC4252-1/LTC4252-2
PI FU CTIO S
VEE (Pin 5/Pin 4): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 6/Pin 5): N-Channel MOSFET Gate Drive Output. This pin is pulled high by a 58A current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV, OV, or a circuit breaker fault timeout. GATE is actively servoed to control the fault current as measured at SENSE. A compensation capacitor at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp-up after an overvoltage event or restart after a current limit fault. During GATE start-up, a second comparator detects if GATE is within 2.8V of VIN before PWRGD is set (MS package only). DRAIN (Pin7/Pin 6): Drain Sense Input. Connecting an external resistor, RD, between this pin and the MOSFET's drain (VOUT) allows voltage sensing below 6.15V and current feedback to TIMER. A comparator detects if DRAIN is below 2.385V and together with the GATE high comparator sets the PWRGD flag. If VOUT is above VDRNCL, DRAIN clamps at approximately VDRNCL. The current through RD is internally multiplied by 8 and added to TIMER's 230A pullup current during a circuit breaker fault cycle. This reduces the fault time and MOSFET heating. OV (Pin 8/Pin7): Overvoltage Input. The active high threshold at the OV pin is set at 6.15V with 0.6V hysteresis. If OV > 6.15V, GATE pulls low. When OV returns below 5.55V, GATE start-up begins without an initial timing cycle. If an overvoltage condition occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after the overvoltage condition goes away. An overvoltage condition does not reset the PWRGD flag. The internal UVLO at VIN always overrides OV. A 1nF to 10nF capacitor at OV prevents transients and switching noise from affecting the OV thresholds and prevents glitches at the GATE pin.
U
U
U
(MS/MS8)
UV (Pin 9/Pin 7): Undervoltage Input. The active low threshold at the UV pin is set at 2.925V with 0.3V hysteresis. If UV < 2.925V, PWRGD pulls high, both GATE and TIMER pull low. If UV rises above 3.225V, this initiates an initial timing cycle followed by GATE start-up. The internal UVLO at VIN always overrides UV. A low at UV resets an internal fault latch. A 1nF to 10nF capacitor at UV prevents transients and switching noise from affecting the UV thresholds and prevents glitches at the GATE pin. TIMER (Pin 10/Pin 8): Timer Input. TIMER is used to generate an initial timing delay at start-up and to delay shutdown in the event of an output overload (circuit breaker fault). TIMER starts an initial timing cycle when the following conditions are met: UV is high, OV is low, VIN clears UVLO, TIMER pin is low, GATE is lower than VGATEL, SS < 0.2V, and VSENSE - VEE < VCB. A pull-up current of 5.8A then charges CT, generating a time delay. If CT charges to VTMRH (4V), the timing cycle terminates, TIMER quickly pulls low and GATE is activated. If SENSE exceeds 50mV while GATE is high, a circuit breaker cycle begins with a 230A pull-up current charging CT. If DRAIN is approximately 7V during this cycle, the timer pull-up has an additional current of 8 * IDRN. If SENSE drops below 50mV before TIMER reaches 4V, a 5.8A pull-down current slowly discharges the CT. In the event that CT eventually integrates up to the VTMRH threshold, the circuit breaker trips, GATE quickly pulls low and PWRGD pulls high. The LTC4252-1 TIMER pin latches high with a 5.8A pull-up source. This latched fault is cleared by either pulling TIMER low with an external device or by pulling UV below 2.925V. The LTC4252-2 the starts a shutdown cooling cycle following an overcurrent fault. This cycle consists of 4 discharging ramps and 3 charging ramps. The charging and discharging currents are 5.8A and TIMER ramps between its 1V and 4V thresholds. At the completion of a shutdown cooling cycle, the LTC4252-2 attempts a start-up cycle.
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9
LTC4252-1/LTC4252-2
BLOCK DIAGRA
VIN
VEE
6.15V
- +
OV *
UV *
-
2.925V VIN
VEE
+ -
LOGIC
230A VIN 5.8A 4V
- +
TIMER
-
VEE 5.8A VIN 22A VEE 1V
FCL
+
SS 95k RSS 5k VEE VEE CB VOS = 10mV
+
ACL
-+ +
-
50mV
+-
VEE
VEE *OV AND UV ARE TIED TOGETHER ON THE MS8 PACKAGE. OV AND UV ARE SEPARATE PINS ON THE MS PACKAGE ** ONLY AVAILABLE IN THE MS PACKAGE
10
+
+
-
-
+
-
+
-
W
DRAIN 2.385V VIN 8x 1x VIN 58A PWRGD ** VIN 58A VEE GATE 2.8V 6.15V 1x VEE 1x
-+
VIN
0.5V
200mV
+-
VEE
VEE SENSE
4252-1/2 BD
425212f
LTC4252-1/LTC4252-2
OPERATIO
Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4252 is designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. Initial Start-Up The LTC4252 resides on a removable circuit board and controls the path between the connector and load or power conversion circuitry with an external MOSFET switch (see Figure 1). Both inrush control and short-circuit protection are provided by the MOSFET. A detailed schematic is shown in Figure 2. - 48V and - 48RTN receive power through the longest connector pins and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV/ OV determines whether or not the MOSFET should be turned on based upon internal high accuracy thresholds and an external divider. UV/OV does double duty by also monitoring whether or not the connector is seated. The top of the divider detects - 48RTN by way of a short connector pin that is the last to mate during the insertion sequence.
PLUG-IN BOARD
LONG -48RTN
LTC4252 LONG -48V BACKPLANE
Figure 1. Basic LTC4252 Hot Swap Topology
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Interlock Conditions A start-up sequence commences once these "interlock" conditions are met. 1. The input voltage VIN exceeds 9.2V (UVLO). 2. The voltage at UV > 3.225V. 3. The voltage at OV < 5.55V. 4. The (SENSE - VEE) voltage is < 50mV (VCB). 5. The voltage at SS is < 0.2V (20 * VOS). 6. The voltage on the TIMER capacitor (CT) is < 1V (VTMRL). 7. The voltage at GATE is < 0.5V (VGATEL). The first three conditions are continuously monitored and the latter four are checked prior to initial timing or GATE ramp-up. Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section. TIMER begins the start-up sequence by sourcing 5.8A into CT. If VIN, UV or OV falls out of range, the start-up cycle stops and TIMER discharges CT to less than 1V, then waits until the aforementioned conditions are once again met. If CT successfully charges to 4V, TIMER pulls low and both SS and GATE pins are released. GATE sources 58A (IGATE), charging the MOSFET gate and associated capacitance. The SS voltage ramp limits VSENSE to control the inrush current. PWRGD pulls active low when GATE is within 2.8V of VIN and DRAIN is lower than VDRNL.
LONG -48RTN RIN 10k 1/2W 1 7 VIN CLOAD 100F TYP
+ +
CLOAD
+
LOW VOLTAGE CIRCUITRY
ISOLATED DC/DC CONVERTER MODULE
+
-
-
4252-1/2 F01
SHORT
R1 402k 1% C1 10nF
CIN 1F
UV/OV LTC4252-1 8 TIMER 2 6 SS DRAIN VEE CSS 68nF CT 0.33F 4 SENSE 3 RC 10 GATE 5 RD 1M
R2 32.4k 1% LONG -48V
CC 18nF RS 0.02
Q1 IRF530S
4252-1/2 F02
Figure 2. -48V, 2.5A Hot Swap Controller
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LTC4252-1/LTC4252-2
OPERATIO
Two modes of operation are possible during the time the MOSFET is first turning on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to -48V and the LTC4252 will fully enhance the MOSFET. A second possibility is that the load current exceeds the softstart current limit threshold of [VSS(t)/20 - VOS]/RS. In this case the LTC4252 will ramp the output by sourcing softstart limited current into the load capacitance. If the softstart voltage is below 1.2V, the circuit breaker TIMER is held low. Above 1.2V, TIMER ramps up. It is important to set the timer delay so that, regardless of which start-up mode is used, the TIMER ramp is less than one circuit breaker delay time. If this condition is not met, the LTC4252-1 may shut down after one circuit breaker delay time whereas the LTC4252-2 may continue to autoretry. Board Removal If the board is withdrawn from the card cage, the UV/OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector. When the power pins subsequently separate, there is no arcing. Current Control Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and resistor RS. There are three distinct thresholds at SENSE: 50mV for a timed circuit breaker function; 100mV for an analog current limit loop; and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. If, owing to an output overload, the voltage drop across RS exceeds 50mV, TIMER sources 230A into CT. CT eventually charges to a 4V threshold and the LTC4252 shuts off. If the overload goes away before CT reaches 4V and SENSE measures less than 50mV, CT slowly discharges (5.8A). In this way the LTC4252's circuit breaker function responds to low duty cycle overloads and accounts for fast heating and slow cooling characteristics of the MOSFET.
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Higher overloads are handled by an analog current limit loop. If the drop across RS reaches 100mV, the current limiting loop servos the MOSFET gate and maintains a constant output current of 100mV/RS. In current limit mode, VOUT typically rises and this increases MOSFET heating. If VOUT > VDRNCL (7V), connecting an external resistor, RD, between VOUT and DRAIN allows the fault timing cycle to be shortened by accelerating the charging of the TIMER capacitor. The TIMER pull-up current is increased by 8 * IDRN. Note that because SENSE > 50mV, TIMER charges CT during this time and the LTC4252 will eventually shut down. Low impedance failures on the load side of the LTC4252 coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/s. Under these conditions, overshoot is inevitable. A fast SENSE comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than the weaker current limit loop. The 100mV/RS current limit loop then takes over and servos the current as previously described. As before, TIMER runs and shuts down the LTC4252 when CT reaches 4V. If CT reaches 4V, the LTC4252-1 latches off with a 5.8A pull-up current source whereas the LTC4252-2 starts a shutdown cooling cycle. The LTC4252-1 circuit breaker latch is reset by either pulling UV momentarily low or dropping the input voltage VIN below the internal UVLO threshold of 8.2V or pulling TIMER momentarily low with a switch. The LTC4252-2 retries after its shutdown cooling cycle. Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hot-swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and CT rejects these events allowing the LTC4252 to "ride out" temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse.
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LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
SHUNT REGULATOR A fast responding regulator shunts the LTC4252 VIN pin. Power is derived from - 48RTN by an external current limiting resistor. The shunt regulator clamps VIN to 13V (VZ). A 1F decoupling capacitor at VIN filters supply transients and contributes a short delay at start-up. RIN should be chosen to accommodate both VIN supply current and the drive required for an optocoupler if the PWRGD function on the 10-pin MS package is used. Higher current through RIN results in higher dissipation for RIN and the LTC4252. An alternative is a separate NPN buffer driving the optocoupler as shown in Figure 3. Multiple 1/4W resistors can replace a single higher power RIN resistor. INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) A hysteretic comparator, UVLO, monitors VIN for undervoltage. The thresholds are defined by VLKO and its hysteresis, VLKH. When VIN rises above 9.2V (VLKO) the chip is enabled; below 8.2V (VLKO - VLKH) it is disabled and GATE is pulled low. The UVLO function at VIN should not be confused with the UV/OV pin(s). These are completely separate functions. UV/OV COMPARATORS An UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds:
GND RIN 10k 1/2W R4 22k Q2 GND (SHORT PIN) 1 R1 432k 1% R2 14k 1% R3 32.4k 1% VIN LTC4252-1 9 8 10 UV OV PWRGD DRAIN GATE VEE 5 SENSE 2 7 6 4 RC 10 CC 18nF RD 1M Q1 IRF530S RS 0.02
4252-1/2 F03
TIMER 3 CT SS 330nF C2 10nF CSS 68nF
-48V * M0C207 Q2: MMBT5551LT1
Figure 3. - 48V/2.5A Application with Wider Input Operating Range
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UV low-to-high (VUVHI) = 3.225V UV high-to-low (VUVLO) = 2.925V An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds: OV low-to-high (VOVHI) = 6.150V OV high-to-low (VOVLO) = 5.550V The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 75V when connected together as in Figure 2. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 402k and R2 = 32.4k gives a typical operating range of 43.2V to 74.4V. The under- and overvoltage shutdown thresholds are then 39.2V and 82.5V. 1% divider resistors are recommended to preserve threshold accuracy. The R1-R2 divider values shown in the Typical Application set a standing current of slightly more than 100A and define an impedance at UV/OV of 30k. In most applications, 30k impedance coupled with 300mV UV hysteresis makes the LTC4252 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. Separate UV and OV pins are available in the 10-pin MS package and can be used for a wider operating range such as 35.5V to 76V as shown in Figure 3. Other combinations are possible with different resistor arrangements.
CL 100F
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CIN 1F
R5 2.2k *
LOAD EN
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LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
UV/OV OPERATION
A low input to the UV comparator will reset the chip and pull the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the other interlock conditions are met. A high-to-low transition in the UV comparator immediately shuts down the LTC4252, pulls the MOSFET gate low and resets the latched PWRGD high. Overvoltage conditions detected by the OV comparator will also pull GATE low, thereby shutting down the load. However, it will not reset the circuit breaker TIMER, PWRGD flag or shutdown cooling timer. Returning the supply voltage to an acceptable range restarts the GATE pin if all the interlock conditions except TIMER are met. Only during the initial timing cycle does an OV condition reset the TIMER. DRAIN Connecting an external resistor, RD, to the dual function DRAIN pin allows VOUT sensing without it being damaged by large voltage transients. Below 6.15V, negligible pin leakage allows a DRAIN low comparator to detect VOUT less than 2.385V (VDRNL). This condition, together with the GATE low comparator, sets the PWRGD flag. If VOUT > VDRNCL (7V), the DRAIN pin is clamped at about 7V and the current flowing in RD is given by:
IDRN
VOUT - VDRNCL RD
This current is scaled up 8 times during a circuit breaker fault and is added to the nominal 230A TIMER current. This accelerates the fault TIMER pull-up when the MOSFET's drain-source voltage exceeds 7V and effectively shortens the MOSFET heating duration. TIMER The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor CT is used at
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TIMER to provide timing for the LTC4252. Four different charging and discharging modes are available at TIMER: 1) A 5.8A slow charge; initial timing and shutdown cooling delay. 2) A (230A + 8 * IDRN) fast charge; circuit breaker delay. 3) A 5.8A slow discharge; circuit breaker "cool off" and shutdown cooling. 4) Low impedance switch; resets the TIMER capacitor after an initial timing delay, in UVLO, in UV and in OV during initial timing. For initial start-up, the 5.8A pull-up is used. The low impedance switch is turned off and the 5.8A current source is enabled when the interlock conditions are met. CT charges to 4V in a time period given by:
t= 4V * C T 5.8A
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(2)
When CT reaches 4V (VTMRH), the low impedance switch turns on and discharges CT. A GATE start-up cycle begins and both SS and GATE are released. CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than a 50mV drop across RS, the TIMER pin charges CT with (230A + 8 * IDRN). If CT charges to 4V, the GATE pin pulls low and the LTC4252-1 latches off while the LTC4252-2 starts a shutdown cooling cycle. The LTC4252-1 remains latched off until the UV pin is momentarily pulsed low or TIMER is momentarily discharged low by an external switch or VIN dips below UVLO and is then restored. The circuit breaker timeout period is given by:
(1)
t=
4V * C T 230A + 8 * IDRN
(3)
If VOUT < 6.15V, an internal PMOS device isolates any DRAIN pin leakage current, making IDRN = 0A in Equation (3). If VOUT > 7V (VDRNCL) during the circuit breaker fault
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LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
period, the charging of CT accelerates by 8 * IDRN of Equation (1). Intermittent overloads may exceed the 50mV threshold at SENSE, but, if their duration is sufficiently short, TIMER will not reach 4V and the LTC4252 will not shut the external MOSFET off. To handle this situation, the TIMER discharges CT slowly with a 5.8A pull-down whenever the SENSE voltage is less than 50mV. Therefore, any intermittent overload with VOUT < 6.15V and an aggregate duty cycle of 2.5% or more will eventually trip the circuit breaker and shut down the LTC4252. Figure 4 shows the circuit breaker response time in seconds normalized to 1F for IDRN = 0A. The asymmetric charging and discharging of CT is a fair gauge of MOSFET heating. The normalized circuit response time is estimated by
t 4 = C T (F ) (235.8 + 8 * IDRN ) * D - 5.8
[
]
10 IDRN = 0A NORMALIZED RESPONSE TIME (s/F)
1 t CT(F) 0.1 = 4 [(235.8 + 8 * IDRN) * D - 5.8]
0.01 0 20 40 60 80 FAULT DUTY CYCLE (%) 100
4252-1/2 F04
Figure 4. Circuit-Breaker Response Time
SHUTDOWN COOLING CYCLE For the LTC4252-1 (latchoff version), TIMER latches high with a 5.8A pull-up after the circuit breaker fault TIMER reaches 4V. For the LTC4252-2 (automatic retry version),
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a shutdown cooling cycle begins if TIMER reaches the 4V threshold. TIMER starts with a 5.8A pull-down until it reaches the 1V threshold. Then, the 5.8A pull-up turns back on until TIMER reaches the 4V threshold. Four 5.8A pull-down cycles and three 5.8A pull-up cycles occur between the 1V and 4V thresholds, creating a time interval given by:
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tSHUTDOWN =
7 * 3V * C T 5.8A
(5)
At the 1V threshold of the last pull-down cycle, a GATE ramp-up is attempted. SOFT-START Soft-start limits the inrush current profile during GATE start-up. Unduly long soft-start intervals can exceed the MOSFET's SOA rating if powering up into an active load. If SS floats, an internal current source ramps SS from 0V to 2.2V in about 220s. Connecting an external capacitor CSS from SS to ground modifies the ramp to approximate an RC response of:
t - R *C VSS (t) VSS * 1 - e SS SS
(4)
(6)
An internal resistor divider (95k/5k) scales VSS(t) down by 20 times to give the analog current limit threshold: VACL (t) = VSS (t) - VOS 20 (7)
This allows the inrush current to be limited to VACL(t)/RS. The offset voltage, VOS (10mV), ensures CSS is sufficiently discharged and the ACL amplifier is in current limit before GATE start-up. SS is pulled low under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out.
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LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
GATE
GATE is pulled low to VEE under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. When GATE turns on, a 58A current source charges the MOSFET gate and any associated external capacitance. VIN limits the gate drive to no more than 14.5V. Gate-drain capacitance (CGD) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at VIN and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value ( 10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. GATE has two comparators: the GATE low comparator looks for < 0.5V threshold prior to initial timing or a GATE start-up cycle; the GATE high comparator looks for < 2.8V relative to VIN and, together with the DRAIN low comparator, sets PWRGD status during GATE startup. SENSE The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. When SENSE exceeds 50mV, the CB comparator activates the 230A TIMER pull-up. At 100mV, the ACL amplifier servos the MOSFET current and, at 200mV, the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists long enough for TIMER to charge CT to 4V (see Equation 3), the LTC4252 shuts down and pulls GATE low. If the SENSE pin encounters a voltage greater than 100mV, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier
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needs time to discharge GATE to the threshold of the MOSFET. For a mild overload the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current. Owing to inductive effects in the system, FCL typically overcorrects the current limit loop and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier to recover. SHORT-CIRCUIT OPERATION Circuit behavior arising from a load side low impedance short is shown in Figure 5 for the LTC4252. Initially, the current overshoots the fast current limit level of VSENSE = 200mV (Trace 2) as the GATE pin works to bring VGS under control (Trace 3). The overshoot glitches the backplane in the negative direction and when the current is reduced to 100mV/RS, the backplane responds by glitching in the positive direction.
SUPPLY RING OWING TO CURRENT OVERSHOOT -48RTN 50V/DIV SUPPLY RING OWING TO MOSFET TURN OFF ONSET OF OUTPUT SHORT-CIRCUIT SENSE 200mV/DIV GATE 10V/DIV TIMER 5V/DIV FAST CURRENT LIMIT ANALOG CURRENT LIMIT CTIMER RAMP LATCH OFF 0.5ms/DIV
4252-1/2 F05
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Figure 5. Output Short-Circuit Behavior of LTC4252
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LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
TIMER commences charging CT (Trace 4) while the analog current limit loop maintains the fault current at 100mV/RS, which in this case is 5A (Trace 2). Note that the backplane voltage (Trace 1) sags under load. Timer pull-up is accelerated by VOUT. When CT reaches 4V, GATE turns off, PWRGD pulls high, the load current drops to zero and the backplane rings up to over 100V. The positive peak is usually limited by avalanche breakdown in the MOSFET and can be further limited by adding a zener diode across the input from - 48V to - 48RTN, such as Diodes Inc. SMAT70A. A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 5 Trace 1, can rob charge from output capacitors on adjacent cards. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4252s are used by the other cards, they respond by limiting the inrush current to a value of 100mV/RS. If CT is sized correctly, the capacitors will recharge long before CT times out. POWER GOOD, PWRGD PWRGD latches low if GATE charges up to within 2.8V of VIN and DRAIN pulls below VDRNL during start-up. PWRGD is reset in UVLO, in a UV condition or if CT charges up to 4V. An overvoltage condition has no effect on PWRGD status. A 58A current pulls this pin high during reset. Due to voltage transients between the power module and PWRGD, optoisolation is recommended. This pin provides sufficent drive for an optocoupler. MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until TIMER times out. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current, but the opposite may not be true. Consult the manufacturer's MOSFET data sheet for safe operating area and effective transient thermal impedance curves.
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MOSFET selection is a 3-step process by assuming the absense of a soft-start capacitor. First, RS is calculated and then the time required to charge the load capacitance is determined. This timing, along with the maximum shortcircuit current and maximum input voltage defines an operating point that is checked against the MOSFET's SOA curve. To begin a design, first specify the required load current and Ioad capacitance, IL and CL. The circuit breaker current trip point (VCB/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at VSUPPLY(MIN). RS is given by:
RS = VCB(MIN) IL(MAX)
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(8)
where VCB(MIN) = 40mV represents the guaranteed minimum circuit breaker threshold. During the initial charging process, the LTC4252 may operate the MOSFET in current limit, forcing (VACL) between 80mV to 120mV across RS. The minimum inrush current is given by:
IINRUSH(MIN)=
80mV RS
(9)
Maximum short-circuit current limit is calculated using the maximum VSENSE. This gives
ISHORTCIRCUIT(MAX)=
120mV RS
(10)
The TIMER capacitor CT must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by:
tCL(CHARGE) =
C * V C L* V SUPPLY(MAX) = I IINRUSH(MIN)
(11)
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LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
The maximum current flowing in the DRAIN pin is given by: IDRN(MAX) V -V = SUPPLY(MAX) DRNCL RD (12)
Approximating a linear charging rate as IDRN drops from IDRN(MAX) to zero, the IDRN component in Equation (3) can be approximated with 0.5 * IDRN(MAX). Rearranging equation, TIMER capacitor CT is given by: CT = tCL(CHARGE) * (230A + 4 * IDRN(MAX) ) 4V (13)
Returning to Equation (3), the TIMER period is calculated and used in conjunction with V SUPPLY(MAX) and ISHORTCIRCUIT(MAX) to check the SOA curves of a prospective MOSFET. As a numerical design example, consider a 30W load, which requires 1A input current at 36V. If VSUPPLY(MAX) = 72V and CL = 100F, RD = 1M, Equation (8) gives RS = 40m; Equation (13) gives CT = 441nF. To account for errors in RS, CT, TIMER current (230A), TIMER threshold (4V), RD, DRAIN current multiplier and DRAIN voltage clamp (VDRNCL), the calculated value should be multiplied by 1.5, giving the nearest standard value of CT = 680nF. If a short-circuit occurs, a current of up to 120mV/ 40m = 3A will flow in the MOSFET for 3.6ms as dictated by CT = 680nF in Equation (3). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms and is safe to use in this application. Computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear MOSFET's SOA characteristics and the RSSCSS response. An overly conservative but simple approach begins with the maximum circuit breaker current, given by:
ICB(MAX)=
60mV RS
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From the SOA curves of a prospective MOSFET, determine the time allowed, tSOA(MAX). CSS is given by:
tSOA(MAX) (15) 0.916 * RSS In the above example, 60mV/40m gives 1.5A. tSOA(MAX) for the IRF530S is 40ms. From Equation (15), CSS = 437nF. Actual board evaluation showed that CSS = 100nF was appropriate. The ratio (RSS * CSS) to tCL(CHARGE) is a good gauge as a large ratio may result in the time-out period expiring. This gauge is determined empirically with board level evaluation. C SS =
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SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 2. It was designed for 50W. Calculate the maximum load current: 50W/36V = 1.4A; allowing for 83% converter efficiency, IIN(MAX) = 1.7A. Calculate RS: from Equation (8) RS = 20m. Calculate I SHORTCIRCUIT(MAX) : from Equation (9) ISHORTCIRCUIT(MAX) = 6A. Select a MOSFET that can handle 6A at 72V: IRF530S. Calculate CT: from Equation (13) CT = 220nF. Select CT = 330nF, which gives the circuit breaker time-out period tMAX = 1.76ms. Consult MOSFET SOA curves: the IRF530S can handle 6A at 72V for 5ms, so it is safe to use in this application. Calculate CSS: using Equations (14) and (15) select CSS = 68nF. FREQUENCY COMPENSATION The LTC4252 typical frequency compensation network for the analog current limit loop is a series RC (10) and CC connected to VEE. Figure 6 depicts the relationship between the compensation capacitor CC and the MOSFET's CISS. The line in Figure 6 is used to select a starting value
(14)
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APPLICATIO S I FOR ATIO
60 COMPENSATION CAPACITANCE CC (nF) 50 40 30 20 10 0 0 2000 4000 6000 MOSFET CISS (pF) 8000
4252-1/2 F06
NTY100N10
SENSE RESISTOR TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER
IRF3710 IRF540 IRF530 IRF740
Figure 6. Recommended Compensation Capacitor CC vs MOSFET CISS
for CC based upon the MOSFET's CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing. As seen in Figure 5 previously, at the onset of a shortcircuit event, the input supply voltage can ring dramatically owing to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche. SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4252's VEE and SENSE pins are strongly recommended. The drawing in Figure 7 illustrates the correct way of making connections between the LTC4252 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation.
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CURRENT FLOW FROM LOAD CURRENT FLOW TO -48V BACKPLANE W
4252-1/2 F07
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TO SENSE
TO VEE
Figure 7. Making PCB Connections to the Sense Resistor
TIMING WAVEFORMS System Power-Up Figure 8 details the timing waveforms for a typical powerup sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At time point 1, the supply ramps up, together with UV/OV, VOUT and DRAIN. VIN and PWRGD follow at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS and TIMER < VTMRL. If all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8A current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < V GATEL , SENSE < V CB and SS < 20 * VOS must be satisfied before a GATE ramp-up cycle begins. SS ramps up as dictated by RSS * CSS (as in Equation 6); GATE is held low by the analog current limit (ACL) amplifier until SS crosses 20 * VOS. Upon releasing GATE, 58A sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET's threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches the SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at
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LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 1 GND - VEE OR (-48RTN) - (-48V) 2 3 4 56 7 8 9 10 11
UV/OV
VIN
VLKO VTMRH
TIMER
5.8A VTMRL
GATE
VGATEL 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS
SS
SENSE
VOUT VDRNCL DRAIN VDRNL
PWRGD INITIAL TIMING GATE START-UP
Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE)
VACL(t) (Equation 7) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE - VEE) reaches the VCB threshold at time point 7, the circuit breaker TIMER activates. The TIMER capacitor, CT, is charged by a (230A + 8 * IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At time point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB, the fault TIMER cycle ends, followed by a 5.8A discharge cycle (cool off). The duration between time points 7 and 9 must be shorter than
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230A + 8 * IDRN 5.8A 58A 58A 5.8A VIN - VGATEH VACL VCB
4252-1/2 F08
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one circuit breaker delay to avoid a fault time out during GATE ramp-up. When GATE ramps past the VGATEH threshold at time point 10, PWRGD pulls low. At time point 11, GATE reaches its maximum voltage as determined by VIN. Live Insertion with Short Pin Control of UV/OV In the example shown in Figure 9, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin. This ensures the power connections are firmly established before the LTC4252 is activated. At time point 1, the power pins make contact and
425212f
LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
UV CLEARS VUVHI, CHECK OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 1 GND - VEE OR (-48RTN) - (-48V) 2 3 4 56 7 8 9 1011
UV/OV
VUVHI
VIN
VLKO VTMRH 230A + 8 * IDRN 5.8A 58A VGATEL 58A 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL VCB 5.8A
TIMER
5.8A VTMRL
GATE
SS
SENSE
VOUT VDRNCL DRAIN VDRNL
PWRGD INITIAL TIMING GATE START-UP
Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE)
VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and its voltage exceeds VUVHI. In addition, the internal logic checks for OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS and TIMER < VTMRL. If all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8A current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL, SENSE < VCB and SS < 20 * VOS must be satisfied before a GATE start-up cycle begins. SS ramps up as dictated by
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VIN - VGATEH
4252-1/2 F09
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RSS * CSS; GATE is held low by the analog current limit amplifier until SS crosses 20 * VOS. Upon releasing GATE, 58A sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET's threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches the SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at VACL(t) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE - VEE) reaches the VCB threshold at time point 7, the circuit breaker TIMER
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21
LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
activates. The TIMER capacitor, CT, is charged by a (230A + 8 * IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB and the fault TIMER cycle ends, followed by a 5.8A discharge cycle (cool off). When GATE ramps past VGATEH threshold at time point 10, PWRGD pulls low. At time point 11, GATE reaches its maximum voltage as determined by VIN. Undervoltage Timing In Figure 10 when UV pin drops below VUVLO (time point 1), the LTC4252 shuts down with TIMER, SS and GATE all pulling low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses.
UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES UV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 1 VUVHI VUVLO VTMRH TIMER 5.8A VTMRL 58A GATE VGATEL 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB VDRNCL DRAIN VDRNL 58A VIN - VGATEH 230A + 8 * IDRN 5.8A 5.8A 2 3 4 56 7 8 9 10 11
UV
SS
PWRGD INITIAL TIMING GATE START-UP
Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE)
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When UV recovers and clears VUVHI (time point 2), an initial timer cycle begins followed by a start-up cycle. VIN Undervoltage Lockout Timing The VIN undervoltage lockout comparator, UVLO, has a similar timing behavior as the UV pin timing except it looks for VIN < (VLKO - VLKH) to shut down and VIN > VLKO to start. In an undervoltage lockout condition, both UV and OV comparators are held off. When VIN exits undervoltage lockout, the UV and OV comparators are enabled. Undervoltage Timing with Overvoltage Glitch In Figure 11, both UV and OV pins are connected together. When UV clears VUVHI (time point 1), an initial timing cycle starts. If the system bus voltage overshoots VOVHI as shown at time point 2, TIMER discharges. At time point 3, the supply voltage recovers and drops below the VOVLO
4252-1/2 F10
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425212f
LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO U
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 1 VOVHI UV/OV VUVHI VTMRH TIMER 5.8A VTMRL 58A GATE VGATEL SS 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB VDRNCL DRAIN VDRNL 58A 230A + 8 * IDRN 5.8A 5.8A 2 3 VOVLO 4 5 67 8 10 12 9 11 VIN - VGATEH GATE START-UP
4252-1/2 F11
UV/OV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE UV/OV DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE
PWRGD INITIAL TIMING
Figure 11. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
threshold. The initial timing cycle restarts, followed by a GATE start-up cycle. Overvoltage Timing During normal operation, if the OV pin exceeds VOVHI as shown at time point 1 of Figure 12, the TIMER and PWRGD status are unaffected. Nevertheless, SS and GATE pull down and the load is disconnected. At time point 2, OV recovers and drops below the VOVLO threshold. A GATE start-up cycle begins. If the overvoltage glitch is long enough to deplete the load capacitor, a full start-up cycle as shown between time points 4 through 7 may occur.
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Circuit Breaker Timing In Figure 13a, the TIMER capacitor charges at 230A if the SENSE pin exceeds VCB but VDRN is less than 6.15V. If the SENSE pin drops below VCB before TIMER reaches the VTMRH threshold, TIMER is discharged by 5.8A. In Figure 13b, when TIMER exceeds VTMRH, GATE pulls down immediately and the LTC4252 shuts down. In Figure 13c, multiple momentary faults cause the TIMER capacitor to integrate and reach VTMRH. GATE pull down follows and the LTC4252 shuts down. During shutdown, the LTC4252-1 latches TIMER high with a 5.8A pull-up current source; the LTC4252-2 activates a shutdown cooling cycle.
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23
LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
1 VOVHI 2 34 OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 5 67 8 9
OV
VOVLO VTMRH
TIMER
230A + 8 * IDRN 58A
GATE
VGATEL
58A 20 * (VACL + VOS)
SS
20 * (VCB + VOS) 20 * VOS VACL VCB GATE START-UP
SENSE
Figure 12. Overvoltage Timing (All Waveforms are Referenced to VEE)
1 VTMRH TIMER
2 VTMRH 5.8A 230A + 8 * IDRN TIMER
GATE
SS VACL SENSE VCB
SENSE
VOUT
DRAIN
DRAIN
PWRGD CB FAULT
PWRGD CB FAULT
(13a) Momentary Circuit-Breaker Fault
(13b) Circuit-Breaker Time Out
Figure 13. Circuit-Breaker Timing Behavior (All Waveforms are Referenced to VEE)
425212f
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5.8A 5.8A VIN - VGATEH
4252-1/2 F12
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CB TIMES OUT 1 2 VTMRH 230A + 8 * IDRN TIMER 1 2 5.8A 3
CB TIMES OUT 4
230A + 8 * IDRN 230A + 8 * IDRN
GATE
GATE
SS VACL VCB
SS VACL SENSE VCB
VOUT VDRNCL
VOUT VDRNCL DRAIN
PWRGD CB FAULT CB FAULT
4252-1/2 F13
(13c) Multiple Circuit-Breaker Fault
LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
Resetting a Fault Latch (LTC4252-1)
The latched circuit breaker fault of LTC4252-1 benefits from long cooling time. It is reset by pulling the UV pin below VUVLO with a switch. Reset is also accomplished by pulling the VIN pin momentarily below (VLKO - VLKH). A third reset method involves pulling the TIMER pin below VTMRL as shown in Figure 14. An initial timing cycle is skipped if TIMER is used for reset. An initial timing cycle is generated if reset by the UV pin or the VIN pin.
SWITCH RESETS LATCHED TIMER SWITCH RELEASES SS 1 5.8A TIMER 2 34 5 67 8 9
VTMRH 230A + 8 * IDRN VTMRL 58A
GATE VGATEL SS
20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL
SENSE
DRAIN
PWRGD GATE START-UP MOMENTARY DPST SWITCH RESET
4252-1/2 F14
Figure 14. Pushbutton Reset of LTC4252-1's Latched Fault (All Waveforms are Referenced to VEE)
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The duration of the TIMER reset pulse should be smaller than the time taken to reach 0.2V at SS pin. With a single pole mechanical pushbutton switch, this may not be feasible. A double pole, single throw pushbutton switch removes this restriction by connecting the second switch to the SS pin. With this method, both the SS and TIMER pins are released at the same time (see Figure 19).
5.8A 5.8A VIN - VGATEH 58A VCB VDRNCL VDRNL
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LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
Shutdown Cooling Cycle (LTC4252-2) Figure 15 shows the timer behavior of the LTC4252-2. At time point 2, TIMER exceeds VTMRH, GATE pulls down immediately and the LTC4252 shuts down. TIMER starts a shutdown cooling cycle by discharging TIMER with 5.8A to the VTMRL threshold. TIMER then charges with 5.8A to the VTMRH threshold. There are four 5.8A
CIRCUIT BREAKER TIMES OUT 1 230A + 8 * IDRN TIMER 2 5.8A 5.8A VTMRL 5.8A 5.8A 5.8A 5.8A
GATE
SS
SENSE
VOUT VDRNCL DRAIN VDRNL
PWRGD SHUTDOWN COOLING GATE START-UP
4252-1/2 F15
CB
Figure 15. Shutdown Cooling Timing Behavior of LTC4252-2 (All Waveforms are Referenced to VEE)
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discharge phases and three 5.8A charge phases in this shutdown cooling cycle spanning time points 2 and 3. At time point 3, the LTC4252 automatic retry occurs with a start-up cycle. Good thermal management techniques are highly recommended; power and thermal dissipation must be carefully evaluated when implementing the automatic retry scheme.
RETRY 3 45 6 78 9 10 VTMRH 230A + 8 * IDRN 5.8A 58A VGATEL 58A 5.8A 5.8A VIN - VGATEH 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL VCB
425212f
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LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
Analog Current Limit and Fast Current Limit In Figure 16a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When SENSE drops below VACL, GATE is allowed to pull up. In Figure 16b, when a severe fault occurs, SENSE exceeds VFCL and GATE immediately pulls down until the analog current amplifier can establish control. If the severe fault
12
34 VTMRH 5.8A 5.8A
230A + 8 * IDRN TIMER
GATE
SS VACL SENSE VCB
VOUT
DRAIN
PWRGD
(16a) Analog Current Limit Fault
Figure 16. Current Limit Behavior (All Waveforms are Referenced to VEE)
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causes VOUT to exceed VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows into the DRAIN pin and is multiplied by 8. This extra current is added to the TIMER pull-up current of 230A. This accelerated TIMER current of [230A+8 * IDRN] produces a shorter circuit breaker fault delay. Careful selection of CT, RD and MOSFET can help prevent SOA damage in a low impedance fault condition.
CB TIMES OUT 1 VTMRH 230A + 8 * IDRN TIMER 2 GATE SS SENSE VFCL VACL VCB VOUT VDRNCL DRAIN PWRGD
4252-1/2 F16
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(16b) Fast Current Limit Fault
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27
LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
Soft-Start If the SS pin is not connected, this pin defaults to a linear voltage ramp, from 0V to 2.2V in about 220s at GATE start-up, as shown in Figure 17a. If a soft-start capacitor, CSS, is connected to this SS pin, the soft-start response is modified from a linear ramp to an RC response (Equation 6), as shown in Figure 17b. This feature allows load current to slowly ramp-up at GATE start-up. Soft-start is initiated at time point 3 by a TIMER transition from VTMRH to VTMRL (time points 1 to 2) or by the OV pin falling below the VOVLO threshold after an OV condition. When the SS pin is below 0.2V, the analog current limit amplifier holds GATE low. Above 0.2V, GATE is released and 58A ramps up the compensation network and GATE capacitance at time point 4. Meanwhile, the SS pin voltage continues to ramp up. When GATE reaches the MOSFET's threshold, the MOSFET begins to conduct. Due to the MOSFET's high gm, the MOSFET current quickly reaches the soft-start
END OF INTIAL TIMING CYCLE 12 34 567 VTMRH TIMER VTMRL 58A GATE 58A 20 * (VACL + VOS) SS 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB VDRNCL DRAIN VDRNL DRAIN SENSE SS 20 * VOS VACL VCB VDRNCL VDRNL VGS(th) VIN - VGATEH 7a 230A + 8 * IDRN 89 10 11 TIMER
5.8A
PWRGD
(17a) Without External CSS
Figure 17. Soft-Start Timing (All Waveforms are Referenced to VEE)
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control value of VACL(t) (Equation 7). At time point 6, the GATE voltage is controlled by the current limit amplifier. The soft-start control voltage reaches the circuit breaker voltage, VCB, at time point 7 and the circuit breaker TIMER activates. As the load capacitor nears full charge, load current begins to decline below VACL(t). The current limit loop shuts off and GATE releases at time point 8. At time point 9, the SENSE voltage falls below VCB and TIMER deactivates. Large values of CSS can cause premature circuit breaker time out as VACL(t) may exceed the VCB potential during the circuit breaker delay. The load capacitor is unable to achieve full charge in one GATE start-up cycle. A more serious side effect of large CSS values is SOA duration may be exceeded during soft-start into a low impedance load. A soft-start voltage below VCB will not activate the circuit breaker TIMER.
END OF INTIAL TIMING CYCLE 12 3 4 5 6 VTMRH VTMRL 58A GATE VGS(th) 58A 20 * (VACL + VOS) 20 * (VCB + VOS) VIN - VGATEH 7 89 10 11 230A + 8 * IDRN 5.8A PWRGD
4252-1/2 F17
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(17b) With External CSS
425212f
LTC4252-1/LTC4252-2
APPLICATIO S I FOR ATIO
Power Limit Circuit Breaker
Figure 18 shows the LTC4252-2 in a power limit circuit breaking application. The SENSE pin is modulated by the board supply voltage, VSUPPLY. The zener voltage, VZ is set to be the same as the low supply operating voltage, VSUPPLY(MIN) = 36V. If the goal is to have the high supply operating voltage, VSUPPLY(MAX) = 72V give the same power at VSUPPLY(MIN), then resistors R4 and R6 are selected using the ratio:
R6 VCB = R4 VSUPPLY(MAX)
If R6 is 22, R4 is 31.6k. The peak circuit breaker power limit is:
POWERMAX
(VSUPPLY(MIN) + VSUPPLY(MAX) )2 =
4 * VSUPPLY(MIN) * VSUPPLY(MAX) *POWERSUPPLY(MIN) = 1.125 * POWERSUPPLY(MIN)
(17)
GND RIN 3x 1.8k 1/4W EACH CIN 1F D1 BZX84C36 2 7 6 4 R6 22 RC 10 CC 18nF RD 1M R4 31.6k
GND (SHORT PIN)
R1 432k 1% R2 14k 1% R3 32.4k 1%
9 8 10 CSS 0.33F C1 10nF 3
UV OV TIMER SS CT 68nF VEE 5
-48V * M0C207
Figure 18. Power Limit Circuit Breaking Application
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when VSUPPLY = 0.5 * (VSUPPLY(MIN) + VSUPPLY(MAX)) = 54V. The peak power at the fault current limit occurs at the supply overvoltage threshold. The fault current limited power is: POWERFAULT = VSUPPLY R6 * VACL - (VSUPPLY - VZ ) * RS R4 (18) (16)
+
CL 100F 1 VIN LTC4252-1 PWRGD DRAIN GATE SENSE R5 5.6k VOUT LOAD EN * Q1 IRF530S RS 0.02
4252-1/2 F18
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425212f
29
LTC4252-1/LTC4252-2
PACKAGE DESCRIPTIO U
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 0.127 (.035 .005) 3.2 - 3.45 (.126 - .136) 0.65 (.0256) BSC 3.00 0.102 (.118 .004) (NOTE 3) 8 7 65 0.52 (.206) REF DETAIL "A" 0 - 6 TYP 4.88 0.1 (.192 .004) 3.00 0.102 (.118 .004) NOTE 4 0.53 0.015 (.021 .006) DETAIL "A" 0.18 (.077) SEATING PLANE 0.22 - 0.38 (.009 - .015) 0.13 0.05 (.005 .002)
MSOP (MS8) 1001
5.23 (.206) MIN
0.42 0.04 (.0165 .0015) TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
1 1.10 (.043) MAX
23
4 0.86 (.034) REF
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.65 (.0256) BCS
425212f
30
LTC4252-1/LTC4252-2
PACKAGE DESCRIPTIO U
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005) 3.2 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF DETAIL "A" 0 - 6 TYP 12345 0.53 0.01 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) 0.13 0.05 (.005 .002)
MSOP (MS) 0402
5.23 (.206) MIN
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
4.88 0.10 (.192 .004)
3.00 0.102 (.118 .004) NOTE 4
1.10 (.043) MAX
0.86 (.034) REF
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.50 (.0197) TYP
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC4252-1/LTC4252-2
TYPICAL APPLICATIO
GND
GND (SHORT PIN)
R1 402k 1% R2 32.4k 1% C1 10nF
-48V
RELATED PARTS
PART NUMBER LT1640AH/LT1640AL LT1641-1/LT1641-2 LTC1642 LT4250 LTC4251/LTC4251-1 LTC4253 DESCRIPTION Negative High Voltage Hot Swap Controllers in SO-8 Positive High Voltage Hot Swap Controllers in SO-8 Fault Protected Hot Swap Controller - 48V Hot Swap Controller in SO-8 - 48V Hot Swap Controllers in SOT-23 -48V Hot Swap Controller with Sequencer COMMENTS Negative High Voltage Supplies from -10V to - 80V Supplies from 9V to 80V, Latched Off/Autoretry 3V to 16.5V, Overvoltage Protection up to 33V Active Current Limiting, Supplies from - 20V to - 80V Fast Active Current Limiting, Supplies from -15V Fast Current Limiting with Three Sequenced Power Good Outputs, Supplies from -15V
32
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
RIN 2x 5.1k IN SERIES 1/4W EACH 1 VIN LTC4252-1 7 8 CT 150nF PUSH RESET 2 UV/OV TIMER SS CSS 27nF VEE 4 DRAIN GATE SENSE 6 5 3 R3 22 RC 10 CC 22nF CIN 1F RD 1M Q1 IRF540S RS 0.01 CL 100F
+
LOAD
VOUT
4252-1/2 F19
Figure 19. - 48V/5A Application
425212f LT/TP 0702 2K PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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